diglot — one IR, two readings

The Verilog you would synthesise and the SMT a solver would see are emitted from the same Design value. They are two denotations of one object, related by mechanised consistency theorems — not two independent translations that happen to agree. Everything below runs in your browser; nothing is sent anywhere.

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source — .dg
netlist denotation → Verilog

    

    

      
transition-system denotation → SMT-LIB

      

    

  






  
simulation — the netlist denotation, executed

  

    A third rendering of the same Design: the simulator evaluates the IR
    directly, and its per-cycle trajectory is checked against the SMT transition system
    cycle by cycle (the differential, ADR-0017 §3). A run below shows a
    trace — one path through the design — not a proof; the proof is the SMT on
    the right. Ghost state is kept here (it is erased from the Verilog): watch
    the ghost lanes move on ghost_fifo.dg.
  


  

    
    
    
    
    
    
  


  

    

      
      
    

    

      

      

      

        ▁▔ 1-bit wire
        ✓ assert holds
        ✗ assert VIOLATED
        ● cover reached
        ⚠ assume broken
        ghost state the Verilog does not keep
      

    

  






  
the exam — official rv32ui, on a core written in .dg

  

    The programs below are not ours: they are assembled from
    riscv-tests'
    isa/rv32ui/*.S, unmodified, and they grade themselves — upstream's
    protocol writes 1 into gp on success and
    (n<<1)|1 naming the sub-test that failed. The core is
    experiments/rv32i-core/core.dg, the same source in the panel above,
    with the test's image in its ROM. It runs here, in your browser, on the
    simulator compiled to wasm — and the design's own asserts are
    checked every cycle on the way, so reaching the right answer by breaking an
    invariant does not count as passing.
    


    40 of upstream's 42 tests pass; 7 are shipped here. The two that do not run
    are ma_data (misaligned stores cross a word and need two writes; the
    memory model has one write port) and fence_i (this core is Harvard).